Static content addressable memory cell

ABSTRACT

A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of each access transistor is coupled to a word line such that when activated, the respective data node and data line are coupled. The CAM cell further includes a match circuit coupled to one of the complementary data nodes of the latch. The match circuit discharges a match line in response to a data value stored at the data node to which the match circuit is coupled and compare data present on the respective data line mismatching. Two of the CAM cells can be used to implement a full ternary CAM cell.

TECHNICAL FIELD

[0001] The present invention is related generally to the field ofsemiconductor memory devices, and more particularly, to static contentaddressable memory cells and methods for storing data therein.

BACKGROUND OF THE INVENTION

[0002] Content addressable memories (CAMs) are used in a variety ofapplications requiring pattern matching operation on bits, such asvirtual memory, data compression, caching, and table lookupapplications. With the popularity of high speed networks, wired orwireless, on the rise, CAMs have been frequently employed in networkingequipment, particularly routers and switches, computer systems and othersystems that require content searching, such as in network-addressfiltering and translation by matching partial node address. For example,in network router or switch, CAM devices are used to store InternetProtocol (IP) addresses and routing instructions associated with eachaddress. When an IP packet is received and the IP address obtained, therouter must retrieve the routing information for the packet in order tosend it on the most direct route to the desired IP address. By using aCAM memory device, the router can search the CAM for the desired IPaddress. That is, the CAM searches for the desired content, and if thereis a match, the CAM returns the associated routing information.

[0003] CAM devices can store data much like conventional memory devices.Generally, an address is provided by a controller to the CAM device, theaddress is used to access a particular memory location within the CAMmemory array, and then the content stored in the addressed memorylocation is retrieved from the memory array. However, as previouslydiscussed, CAM devices provide the added functionality of being able tosearch the stored data for desired content. That is, in addition tosimply storing data in its memory array, a CAM device can search thememory array based on compare data corresponding to the desired content.When the content stored in the CAM memory array does not match thecompare data, the CAM device returns a no match indication. However,when the content stored in the CAM memory array matches the comparedata, the CAM device outputs information associated with the content.

[0004] CAM storage cells have been implemented using dynamic randomaccess memory (DRAM) cells, as well as static random access memory(SRAM) cells. One of the benefits of using a DRAM cell structure for CAMcells is that they are smaller in size relative to SRAM cells. However,as with conventional DRAM cells, such designed CAM cells need to beperiodically refreshed in order to maintain the integrity of the data,as is well known. CAM devices designed with DRAM cells also require thatthe rows of the CAM device to be read sequentially, one row at a time,which is prohibitively slow. Moreover, due to the match circuit that isincluded with CAM cells, there are more leakage paths from the storagenode. The techniques used in DRAM cells to reduce transfer gate leakagemay not be readily available to CAM cell designs.

[0005] As previously mentioned, CAM cells have also been implementedusing SRAM cell designs. Although larger in size than DRAM cells, SRAMcells provide the benefit of not needing to be refreshed to maintaindata integrity. SRAM cells have been designed with six transistors (6T)as well as four transistors (4T). The 6T SRAM cells provide the benefitof having relatively low soft-error rates. “Soft-errors,” as known inthe art, are those errors that are typically caused by power supplyproblems or alpha particles. Although 4T SRAM cells are smaller relativeto their 6T counterparts, the 4T SRAM cells have higher soft-errorrates. This issue is particularly significant with respect to CAMdevices, since the data stored in the CAM memory array essentiallyrepresents a database of information. That is, the soft-error rate ofconventional 4T SRAM cells may be unacceptable in the application of aCAM device. Consequently, choosing to design a CAM device using a 6TSRAM structure, which, as previously mentioned, are relatively larger,may be an acceptable compromise in light of the more significant issuesthat arise where the integrity of the data in the CAM cell isquestionable.

[0006] Accordingly, there is a desire and need for an alternative CAMcell design that is relatively small and yet has acceptably lowsoft-error rates.

SUMMARY OF THE INVENTION

[0007] The present invention is directed to a static content addressablememory (CAM) cell. The CAM cell includes a latch having complementarydata nodes capacitively coupled to ground, first and second accesstransistors, each coupled between a data node of the latch and arespective data line. The gates of each access transistor is coupled toa word line such that when activated, the respective data node and dataline are coupled. The CAM cell further includes a match circuit coupledto one of the complementary data nodes of the latch. The match circuitdischarges a match line in response to a data value stored at the datanode to which the match circuit is coupled and compare data present onthe respective data line mismatching. Two of the CAM cells can be usedto implement a full ternary CAM cell. In storing data in the CAM cell, afirst one of the data nodes is charged and the other data node iscoupled to ground. The capacitive coupling of the first data nodeassists in is maintained the charge state.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a block diagram of a content addressable memory (CAM)device having a CAM array including CAM memory cells according to anembodiment of the present invention

[0009]FIG. 2 is a schematic drawing of a CAM memory cell according to anembodiment of the present invention.

[0010]FIG. 3 is a schematic drawing of a CAM memory cell according to analternative embodiment of the present invention.

[0011]FIG. 4 is a schematic drawing of a CAM memory cell according to analternative embodiment of the present invention.

[0012]FIG. 5 is a block diagram of a computer system including a contentaddressable memory device according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0013] Embodiments of the present invention are directed to staticcontent addressable memory cells and methods of storing data therein.Certain details are set forth below to provide a sufficientunderstanding of the invention. However, it will be clear to one skilledin the art that the invention may be practiced without these particulardetails. In other instances, well-known circuits, control signals, andtiming protocols have not been shown in detail in order to avoidunnecessarily obscuring the invention.

[0014]FIG. 1 illustrates a content addressable memory (CAM) 100 having aCAM array 104 that includes CAM memory cells according to an embodimentof the present invention. The content addressable memory 100 furtherincludes an input/output (I/O) buffer 108 that is coupled to a bus 110on which various data is provided to and from the CAM 100, such ascommand data, address data, data values, and the like. Data output bythe CAM 100 are also provided from the I/O buffer onto the bus 110. TheI/O buffer 108 further serves the function of providing the datareceived to the appropriate block of the CAM 100. For example, commanddata received at the I/O buffer is provided on a command bus 112 tocontrol logic 114. The command data received by the control logic 114 isthen translated into internal timing and data signals that control thefunctionality of the CAM 100. The control logic 114 may further includeslogic circuitry to provide enhanced functionality. Address data providedto the I/O buffer is provided to an address decoder 120 from the controllogic 114 on an address bus 124. The address data is decoded and theappropriate rows of memory cells of the CAM array 104 are activated foraccessing. Where data is being written to the memory cells of the CAMarray 104, data values are provided by the I/O buffer 108 to the CAMarray 104 on a data bus 130. Data read from the CAM array 104 isprovided on the data bus 130 to the I/O buffer 108.

[0015] Where the CAM 100 is commanded to perform a matching operation,compare data values representing the data pattern to match are providedby the I/O buffer on the data bus 130 to a comparand register 140. Amask register 142 is loaded with a mask value that can be used toindicate which bits of the data pattern are significant in the matchoperation. Upon the control block issuing the appropriate signals, amatching operation is performed that simultaneously compares data storedin the CAM array 104 with the data pattern stored in the comparandregister 140. Every row of the CAM array 104 having data matching thedata pattern is then provided to a priority encoder block 146 where amatched entry index is generated based on the match results. The matchedentry index determined by the priority encoder block 146 is thenprovided as output data from the CAM 100.

[0016] It will be appreciated that the CAM 100 illustrated in FIG. 1 hasbeen provided by way of example, and that the previous discussion was ageneral description provided for the benefit of the reader. Those ofordinary skill in the art have sufficient understanding of the operationand functionality of CAM devices such that FIG. 1 and the accompanyingdescription is sufficient to enable those of ordinary skill in the artto practice embodiments of the present invention. Consequently, a moredetailed description of the CAM 100 has been omitted from herein in theinterest of brevity.

[0017]FIG. 2 illustrates a CAM memory cell 200 according to anembodiment of the present invention, and which can be used in the CAMarray 104 of FIG. 1. The CAM memory cell 200 includes a cell 210 havingcomplementary data nodes 212 and 214 coupled to complementary data lines270 and 271 through transfer gates 216 and 218, all respectively. Gatesof both the transfer gates 216 and 218 are coupled to a word line 272 sothat when the word line 272 is activated, the transfer gates 216 and 218couple the data nodes 212 and 214 to respective data lines 270 and 271.The cell 210 further includes a bistable circuit 230 havingcross-coupled transistors 232 and 234 and resistors 222 and 224 coupledto a respective one of the data nodes 212 and 214. The resistors 222 and224 are also coupled to a power supply to provide charge to the datanodes 212 and 214, and the bistable circuit 230 is further coupled to aground. The bistable circuit 230 can be set into one of two states tostore complementary data at the data nodes 212 and 214. Capacitors 240and 242 are coupled between a respective one of the data nodes 212 and214 and ground. As will be explained in more detail below, thecapacitors 240 and 242 provide the CAM memory cell 200 with improvedsoft-error rate and improved data integrity while allowing for a compactCAM memory cell structure.

[0018] The CAM memory cell 200 further includes a match circuit 250coupled to the data nodes 212 and 214. A transistor 252 has a gatecoupled to the data node 212 and is used to selectively couple the dataline 270 to a gate of a transistor 254. Similarly, a transistor 253 hasa gate coupled to the data node 214 and is used to selectively couplethe data line 271 to the gate of the transistor 254. The transistor 254is used to discharge a match line 260 to a LOW logic level, which isindicative of a mismatch of search data applied to the data line 270 andthe data stored by the cell 210.

[0019] In operation, read and write operations of the CAM memory cell200 are similar to conventional SRAM memory devices, with the exceptionthat the match line 260 is always held at a LOW logic level during theoperation.

[0020] To write data to the CAM memory cell 200, the word line 272 isheld at a LOW logic level until the data line 270 is precharged to thelogical level of an input data bit and data line 271 is precharged tothe complement logical level. The voltage of the word line 272 is thenraised to activate the transfer gates 216 and 218 to update the storedvalue at the data nodes 212 and 214, respectively, with the value of theinput data bit. The capacitor coupled to the data node having a HIGHlogic level applied to it will be charged, and the transistor coupled tothe opposite data node will be activated to couple that data node toground, thereby setting the bistable circuit 230 into one of its twostates. The word line is then deactivated to isolate the data nodes 212and 214 from the data lines 270 and 271 to store the updated value. Thecharge on the capacitor that is coupled to the data node storing a HIGHlogic level will be maintained by the resistive current path from thepower supply. By having capacitors 240 and 242 coupled to a respectivedata node, stored data can be maintained with greater integrity becausethe charge on the respective data nodes 212 and 214 is less susceptibleto variability. Consequently, the cell 210 is more resistant tosoft-errors, such as those errors that can be caused by power supplyproblems or alpha particles, and to which small dimensioned memory cellsare particularly susceptible.

[0021] To read data from the CAM memory cell 200, the word line 272 isheld at a LOW logic level until the data lines 270 and 271 are bothprecharged. The word line is then activated to couple the data nodes 212and 214 to the respective data line 270 and 271. The change in thepotential of the data lines 270 and 271, due to the charge transferbetween the data nodes 212 and 214 and the data lines 270 and 271, issensed in a conventional manner and amplified to provide output data.

[0022] With respect to a match operation for the CAM memory cell 200,the match circuit 250 compares the data stored at the data node 212 to acompare data value provided by the data line 270. In the CAM memory cell200, the compare data is the complement data value. That is, if thecompare data is a LOW logic value, a match will be indicated when a HIGHlogic value is stored at the node 212. Generally, the match operationproceeds as follows. The word line 272 is held to a LOW logic level. Thematch line 260 is precharged to a HIGH logic level and the data line 270is set to a compare data value. Consequently, the data line 271 is setto the complementary logic level of the data line 270. If there is amismatch between the compare data value on the data line 270 and thedata value stored at the node 212, the match line 260 is discharged to aLOW logic level.

[0023] For example, assuming that a LOW logic level is stored at thedata node 212 and the compare data value on the data line 270 is a LOWlogic level. In this case, the data node 214 is at a HIGH logic level,and the data line 271 is also at a HIGH logic level. Under theseconditions, the transistor 253 is ON, coupling the HIGH logic level ofthe data line 271 to the gate of the transistor 254. The conductivestate of the transistor 254 provides a current path to ground throughwhich the match line 260 is discharged from its precharged state. Wherethe data node 212 is at a LOW logic level, and the data line 270 is at aHIGH logic level, although the transistor 253 is switched ON, the matchline 260 remains at a HIGH logic level because the data line 271 is at aLOW logic level, thus, the transistor 254 remains OFF.

[0024]FIG. 3 illustrates a CAM memory cell 300 according to analternative embodiment of the present invention. The CAM memory cell 300is a full-ternary CAM memory cell having three different matchconditions: match, mismatch, and “don't care.” The CAM memory cell 300implements the following truth table: 370a, 371a, DL_A DL_B 312a, CELL_A312b, CELL_B 360, MATCH X X 0 0 1 0 0 X X 1 1 0 0 1 1 0 1 1 0 1 1 0 1 00 0 1 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0

[0025] The CAM memory cell 300 includes two CAM subcells 302 a and 302b. It will be appreciated that elements that are identical in the CAMsubcells 302 a and 302 b have the same reference number, except that an“a” or “b” has been added to identify to which CAM subcell the elementbelongs. The following description is made with respect to the CAMsubcell 302 a, however, it will be appreciated that the description canbe applied to the CAM subcell 302 b as well.

[0026] The CAM subcell 302 a includes a cell 310 a having complementarydata nodes 312 a and 314 a coupled to complementary data lines 370 a and371 a through transfer gates 316 a and 318 a, all respectively. Gates ofboth the transfer gates 316 a and 318 a are coupled to a word line 372so that when the word line 372 is activated, the transfer gates 316 aand 318 a couple the data nodes 312 a and 314 a to respective data lines370 a and 371 a. The cell 310 a further includes a bistable circuit 330a having cross-coupled transistors 332 a and 334 a and resistors 322 aand 324 a coupled to a respective one of the data nodes 312 a and 314 a.The resistors 322 a and 324 a are also coupled to a power supply toprovide charge to the data nodes 312 a and 314 a, and the bistablecircuit 330 a is further coupled to ground. The bistable circuit 330 scan be set into one of two states to store complementary data at thedata nodes 312 a and 314 a. Capacitors 340 a and 342 a are coupledbetween a respective one of the data nodes 312 a and 314 a and ground.As will be explained in more detail below, the capacitors 340 a and 342a provide the CAM subcell 302 a with improved soft-error rate andimproved data integrity while allowing for a compact CAM memory cellstructure.

[0027] The read and write operations for the CAM memory cell 300 aresimilar to read and write operations previously described with respectto the CAM memory cell 200, and will not repeated here in the interestof brevity.

[0028] With respect to a match operation for the CAM memory cell 300,the match circuit 350 a and 350 b compare the data stored at the datanodes 312 a and 312 b, respectively, to compare data values provided bythe data lines 370 a and 370 b. For the CAM memory cell 300, the comparedata is the complement of the data value stored at the respective datanode. That is, if the compare data is a LOW logic value for the dataline 370 a and a HIGH logic value for the data line 370 b, a match willbe indicated when a HIGH logic value is stored at the node 312 a and aLOW logic value is stored at the node 312 b. Generally, in operation theword line 372 is held to a LOW logic level for the match operation. Thematch line 360 is precharged to a HIGH logic level and the data lines370 a and 370 b are set to a compare data value. The data lines 371 aand 371 b are not used during the match operation. As will be explainedin more detail below, the logic level of the match line 360 followingthe comparison of the compare data values and the stored data isindicative of the match condition, that is, whether there is a match ordon't care, or a mismatch.

[0029] With the CAM memory cell 300, there are two don't care conditionswith the CAM memory cell 300. That is, whether the stored data and thecompare data match or not will not affect the logic level of the matchline 360. The first don't care condition exists where the compare dataprovided to both the data lines 370 a and 370 b are at a LOW logiclevel. The second don't care condition exists where the data stored atboth the data nodes 312 a and 312 b, is at a LOW logic level. Thus, toinvoke a don't care condition for the CAM memory cell 300, either thecompare data or stored data for both CAM subcells 302 a and 302 b shouldbe at a LOW logic level. In either of the don't care conditions, thematch line 360 is maintained at a HIGH logic level. Similarly, wherethere is a match between the compare data and the stored data for bothCAM subcells 302 a and 302 b, the match line 360 will be kept at a HIGHlogic level indicating a match. However, the match line 360 will bedischarged to a LOW logic level, indicating a data mismatch, when thereis a mismatch between the compare data and the stored data for either ofthe CAM subcells 302 a and 302 b. Under these conditions, at least oneof the transistors 354 a or 354 b is activated to discharge the matchline 360.

[0030] For example, assume that the data condition for the CAM subcells302 a and 302 b is “10.” That is, the data node 312 a is at a HIGH logiclevel and the data node 312 b is at a LOW logic condition. Under thisdata condition, the transistor 352 a is ON and the transistor 352 b isOFF. In the event that the compare data condition is “01,” the data line370 a is at a LOW logic level and the data line 370 b is at a HIGH logiclevel. As a result, although the transistor 352 a is conductive, thematch line 360 is not discharged since the transistor 354 a remains OFFdue to the LOW logic level present on the data line 370 a. With respectto the transistor 354 b, it remains OFF although the data line 370 b isat a HIGH logic level because the transistor 352 b is OFF due to the LOWlogic level of the data node 312 b. Consequently, the match line 360remains at a HIGH logic level indicating that there is a data match.

[0031] In contrast, in the event that the compare data condition is“10,” the data line 370 a is at a HIGH logic level and the data line 370b is at a LOW logic level. As a result, the transistor 354 a is madeconductive because the transistor 352 a is ON based on the HIGH logiclevel stored at the node 312 a, and the HIGH logic level of the dataline 370 a is applied to the gate of the transistor 354 a to switch itON. The transistor 354 a provides a current path to ground through whichthe match line 360 is discharged to a LOW logic level, thus indicating adata mismatch. Similarly, where the compare data condition is “11,”again the transistor 354 a is ON providing a current discharge path topull the match line 360 to a LOW logic level.

[0032] As previously discussed, a don't care condition exists where thedata condition is “00” or the compare data condition is “00.” In thefirst case, where the data condition is “00,” neither one of thetransistors 354 a or 354 b are conductive because both the transistors352 a and 352 b are OFF, thereby isolating the gates of the transistors354 a and 354 b from whatever the logic level is on the data lines 370 aand 370 b. Similarly, in the second case, where the compare datacondition is “00,” both of the transistors 354 a and 354 b remain OFFregardless of the data condition because even if one of the transistors352 a or 352 b were conductive to couple the data lines 370 a and 370 bto the gate of a respective transistor 354 a or 354 b, the LOW logiccondition would keep the transistors 354 a and 354 b OFF. As a result,in either don't care condition, the match line 360 is maintained at aHIGH logic level.

[0033]FIG. 4 is a CAM memory cell 400 according to another embodiment ofthe present invention. The CAM memory cell 400 is identical to the CAMmemory cell 300 of FIG. 3, except that the match circuits for the twoembodiments are different. Similar reference numbers have been used inFIGS. 3 and 4 to indicate similar elements in the CAM memory cell 300and 400. In the CAM memory cell 400, match circuits 380 a and 380 b eachinclude a first discharge transistor 382 having a gate coupled to therespective data node, and a second discharge transistor 384 having agate coupled to the respective data line. The two discharge transistors382 and 384 provide a current path to ground for the match line to bedischarged under the right data and compare data conditions. Operationof the CAM memory cell 400 is the same as for the CAM memory cell 300,as previously described.

[0034] Although operation of the CAM memory cells 300 and 400 is nearlythe same, the CAM memory cell 300 may provide some advantage over theCAM memory cell 400 with respect to the time to indicate a mismatch.That is, in the CAM memory cell 300, the discharge path through whichthe match line 360 is discharged to ground, which indicates a datamismatch, is through a single transistor, namely, the transistor 354. Incontrast, the discharge path through which the match line 360 isdischarged to ground in the CAM memory cell 400 is through twotransistors in series, namely, the transistors 382 and 384. Dischargingthe match line 360 through the two transistors 382 and 384 willgenerally be slower than discharging the match line through only the onetransistor 354. As a result, the matching operation will consequentlytake longer to complete. However, there may be some benefits from usingthe CAM memory cell 400, such as greater resistance to current leakagefrom the match line 360 to ground.

[0035]FIG. 5 illustrates a processor-based system 500 including a CAMdevice 504 in accordance with an embodiment of the present invention.The processor-based system 500 represents a system that utilizes a CAMdevice 504, such as a computer system, a network switch, network router,process control system, or the like. The processor-based system 500includes a central processing unit (CPU) 502 in communication with theCAM 504 over a bus 512. It will be appreciated that the bus 512 can berepresentative of a series of buses and bridges commonly used inprocessor-based systems. However, for the sake of convenience, only thebus 512 has been illustrated in FIG. 5. In addition, the processor-basedsystem 500 includes one or more input devices 506, such as a keyboard ora mouse, coupled to the CPU 502 to allow an operator to interface withthe CPU 502. Typically, the processor-based system 500 also includes oneor more output devices 508 coupled to the CPU 502. Such output devicestypically include printers or a video terminal. One or more data storagedevices 510 are also typically coupled to the CPU 502 to store data orretrieve data from external storage media (not shown). Examples oftypical storage devices 510 include hard and floppy disks, tapecassettes, and compact disc read-only memories (CD-ROMs). Theprocessor-based system 500 also includes a memory device 514, such as arandom access memory (RAM) or a read-only memory (ROM). The CPU 502 iscoupled to the memory device 514 through a bus 516, that typicallyincludes appropriate address, data, and control busses to provide forwriting data to and reading data from the memory device 502.

[0036] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. In a content addressable memory (CAM) array having CAM cells arrangedin rows of word lines and columns of data lines, a CAM cell, comprising:a bistable circuit coupled to a power supply and ground, the bistablecircuit having first and second data nodes; first and second accesstransistors coupled to the first and second data nodes and first andsecond data lines, all respectively, for coupling the respective datanode to the respective data line in response to activating a word line;first and second capacitors, each capacitor having a first terminalcoupled to a respective data node and having a second terminal coupledto ground; and a match circuit having a search node coupled to the firstdata line, a cell node coupled to the first data node, and a match nodecoupled to a match line, the match circuit changing the logic state ofthe match line in response to search data provided on the first dataline and the data stored at the first data node are mismatching.
 2. TheCAM array of claim 1 wherein the match circuit comprises: first andsecond transistors coupled in series between the first and second datalines, the first transistor having a gate coupled to the first data nodeand the second transistor having a gate coupled to the second data node;and a discharge transistor coupled between the match line and ground,and having a gate coupled to a node between the first and secondtransistors.
 3. The CAM cell of claim 1 wherein the bistable circuitcomprises: a first switch having a first node coupled to the first datanode, a second node coupled to ground, and a control node coupled to thesecond data node; a second switch having a first node coupled to thesecond data node, a second node coupled to ground, and a control nodecoupled to the first data node; and first and second resistors, eachresistor having a first terminal coupled to the power supply and asecond terminal coupled to a respective data node.
 4. The CAM cell ofclaim 1 wherein the first and second data nodes store complementarydata, and the first and second data lines are a pair of complementarydata lines.
 5. The CAM cell of claim 1 wherein the search data and thedata stored at the first data node are mismatching when the logic levelof each are the same.
 6. In a content addressable memory (CAM) arrayhaving CAM cells arranged in rows of word lines and columns of datalines, a CAM cell, comprising: a first bistable circuit coupled to apower supply and ground, the first bistable circuit having first andsecond data nodes; a second bistable circuit coupled to the power supplyand ground, the second bistable circuit having third and fourth datanodes; first and second access transistors coupled to the first andsecond data nodes and first and second data lines, all respectively, forcoupling the respective data node to the respective data line inresponse to activating a word line; second and fourth access transistorscoupled to the third and fourth data nodes and third and fourth datalines, all respectively, for coupling the respective data node to therespective data line in response to activating the word line; first,second, third, and fourth capacitors, each capacitor having a firstterminal coupled to a respective data node and having a second terminalcoupled to ground; and a match circuit having a first search nodecoupled to the first data line and a second search node coupled to thethird data line, a first cell node coupled to the first data node and asecond cell node coupled to the third data node, and a match nodecoupled to a match line, the match circuit changing the logic state ofthe match line in response to search data provided on the first dataline and the first data node mismatch and search data provided on thethird data line and the third data node mismatch.
 7. The CAM cell ofclaim 6 wherein the match circuit comprises first, second, third, andfourth switches, each switch having a control node and first and secondnodes, the first switch having its first node coupled to ground and itssecond node coupled to the match line, and the second switch having itsfirst node coupled to the first data line, its second terminal coupledto the control terminal of the first switch, and its control nodecoupled to the first data node, and the third switch having its firstnode coupled to ground and its second node coupled to the match line,and the fourth switch having its first node coupled to the third dataline, its second terminal coupled to the control terminal of the thirdswitch, and its control node coupled to the third data node.
 8. The CAMcell of claim 6 wherein the match circuit comprises first, second,third, and fourth switches, each switch having a control node and firstand second nodes, the first switch having its control terminal coupledto the first data node and its first node coupled to ground, the secondswitch having its control terminal coupled to the first data line, itsfirst node coupled to the match line, and its second node coupled to thesecond node of the first transistor, and the third switch having itscontrol terminal coupled to the third data node and its first nodecoupled to ground, the fourth switch having its control terminal coupledto the third data line, its first node coupled to the match line, andits second node coupled to the second node of the third transistor. 9.The CAM cell of claim 6 wherein the first and second bistable circuitscomprise: a first switch having a first node coupled to a true datanode, a second node coupled to ground, and a control node coupled to anot data node; a second switch having a first node coupled to the notdata node, a second node coupled to ground, and a control node coupledto the true data node; a first resistor having a first terminal coupledto the power supply and a second terminal coupled to the true data node;and a second resistor having a first terminal coupled to the powersupply and a second terminal coupled to the not data node.
 10. The CAMcell of claim 6 wherein the first and second data nodes storecomplementary data, the first and second data lines are a pair ofcomplementary data lines, the third and fourth data nodes storecomplementary data, and the third and fourth data lines are a pair ofcomplementary data lines.
 11. The CAM cell of claim 6 wherein the searchdata and the data stored at the first data node are mismatching when thelogic level of each are the same.
 12. A static content addressablememory array for a content addressable memory (CAM) device, comprising:a plurality of word lines; a plurality of data lines; a latch havingcomplementary data nodes capacitively coupled to ground; first andsecond access transistors, each having a gate coupled to one of theplurality of word lines and coupled between a data node of the latch anda respective data line of the plurality; and a match circuit coupled toone of the complementary data nodes of the latch, the match circuitdischarging a match line in response to a data value stored at the datanode to which the match circuit is coupled and compare data present onthe respective data line mismatching.
 13. The static CAM array of claim12 wherein the match circuit comprises: first and second transistorscoupled in series between the data lines to which the first and secondaccess transistors are coupled, the first transistor having a gatecoupled to a first one of the data nodes and the second transistorhaving a gate coupled to a second one of the complementary data nodes;and a discharge transistor coupled between the match line and ground,and having a gate coupled to a node between the first and secondtransistors.
 14. The static CAM array of claim 12 wherein the latch is afirst latch, the match circuit is a first match circuit, and the staticCAM array further comprises: a second latch having complementary datanodes capacitively coupled to ground, the first and second latchesrepresenting a single CAM memory cell; third and fourth accesstransistors, each having a gate coupled to the word line to which thefirst and second access transistors are coupled, the third and fourthaccess transistors coupled between a data node of the second latch and arespective data line of the plurality; and a second match circuitcoupled to one of the complementary data nodes of the second latch, thematch circuit discharging the match line in response to a data valuestored at the data node to which the second match circuit is coupled andcompare data present on the respective data line mismatching.
 15. Thestatic CAM array of claim 14 wherein the first and second match circuitscomprise first and second switches, each switch having a control nodeand first and second nodes, the first switch having its first nodecoupled to ground and its second node coupled to the match line, and thesecond switch having its first node coupled to the first data line, itssecond terminal coupled to the control terminal of the first switch, andits control node coupled to the first data node.
 16. The static CAMarray of claim 14 wherein the first and second match circuits comprisefirst and second switches, each switch having a control node and firstand second nodes, the first switch having its control terminal coupledto the first data node and its first node coupled to ground, the secondswitch having its control terminal coupled to the first data line, itsfirst node coupled to the match line, and its second node coupled to thesecond node of the first transistor.
 17. The static CAM array of claim12 wherein the latch comprises: a first switch having a first nodecoupled to a first of the complementary data nodes, a second nodecoupled to ground, and a control node coupled to the second data node; asecond switch having a first node coupled to the second data node, asecond node coupled to ground, and a control node coupled to the firstdata node; and first and second resistors, each resistor having a firstterminal coupled to the power supply and a second terminal coupled to arespective data node.
 18. A content addressable memory (CAM) device,comprising: an address bus; a control bus; a data bus; an addressdecoder coupled to the address bus; a read/write circuit coupled to thedata bus; and an array of CAM memory cells coupled to the addressdecoder, control circuit, and read/write circuit, the array comprising:a plurality of word lines; a plurality of data lines; a latch havingcomplementary data nodes capacitively coupled to ground; first andsecond access transistors, each having a gate coupled to one of theplurality of word lines and coupled between a data node of the latch anda respective data line of the plurality; and a match circuit coupled toone of the complementary data nodes of the latch, the match circuitdischarging a match line in response to a data value stored at the datanode to which the match circuit is coupled and compare data present onthe respective data line mismatching.
 19. The CAM device of claim 18wherein the match circuit of the array of CAM memory cells comprises:first and second transistors coupled in series between the data lines towhich the first and second access transistors are coupled, the firsttransistor having a gate coupled to a first one of the data nodes andthe second transistor having a gate coupled to a second one of thecomplementary data nodes; and a discharge transistor coupled between thematch line and ground, and having a gate coupled to a node between thefirst and second transistors.
 20. The CAM device of claim 18 wherein thelatch of the array of CAM memory cells is a first latch, the matchcircuit is a first match circuit, and the static CAM array furthercomprises: a second latch having complementary data nodes capacitivelycoupled to ground, the first and second latches representing a singleCAM memory cell; third and fourth access transistors, each having a gatecoupled to the word line to which the first and second accesstransistors are coupled, the third and fourth access transistors coupledbetween a data node of the second latch and a respective data line ofthe plurality; and a second match circuit coupled to one of thecomplementary data nodes of the second latch, the match circuitdischarging the match line in response to a data value stored at thedata node to which the second match circuit is coupled and compare datapresent on the respective data line mismatching.
 21. The CAM device ofclaim 20 wherein the first and second match circuits of the array of CAMmemory cells comprise first and second switches, each switch having acontrol node and first and second nodes, the first switch having itsfirst node coupled to ground and its second node coupled to the matchline, and the second switch having its first node coupled to the firstdata line, its second terminal coupled to the control terminal of thefirst switch, and its control node coupled to the first data node. 22.The CAM device of claim 20 wherein the first and second match circuitsof the array of CAM memory cells comprise first and second switches,each switch having a control node and first and second nodes, the firstswitch having its control terminal coupled to the first data node andits first node coupled to ground, the second switch having its controlterminal coupled to the first data line, its first node coupled to thematch line, and its second node coupled to the second node of the firsttransistor.
 23. The CAM device of claim 18 wherein the latch of thearray of CAM memory cells comprises: a first switch having a first nodecoupled to a first of the complementary data nodes, a second nodecoupled to ground, and a control node coupled to the second data node; asecond switch having a first node coupled to the second data node, asecond node coupled to ground, and a control node coupled to the firstdata node; and first and second resistors, each resistor having a firstterminal coupled to the power supply and a second terminal coupled to arespective data node.
 24. A content addressable memory (CAM) device,comprising: an address bus; a control bus; a data bus; an addressdecoder coupled to the address bus; a read/write circuit coupled to thedata bus; and an array of CAM memory cells coupled to the addressdecoder, control circuit, and read/write circuit, each CAM cellcomprising: a first bistable circuit coupled to a power supply andground, the first bistable circuit having first and second data nodes; asecond bistable circuit coupled to the power supply and ground, thesecond bistable circuit having third and fourth data nodes; first andsecond access transistors coupled to the first and second data nodes andfirst and second data lines, all respectively, for coupling therespective data node to the respective data line in response toactivating a word line; second and fourth access transistors coupled tothe third and fourth data nodes and third and fourth data lines, allrespectively, for coupling the respective data node to the respectivedata line in response to activating the word line; first, second, third,and fourth capacitors, each capacitor having a first terminal coupled toa respective data node and having a second terminal coupled to ground;and a match circuit having a first search node coupled to the first dataline and a second search node coupled to the third data line, a firstcell node coupled to the first data node and a second cell node coupledto the third data node, and a match node coupled to a match line, thematch circuit changing the logic state of the match line in response tosearch data provided on the first data line and the first data nodemismatch and search data provided on the third data line and the thirddata node mismatch.
 25. The CAM device of claim 24 wherein the matchcircuit of the CAM cell comprises first, second, third, and fourthswitches, each switch having a control node and first and second nodes,the first switch having its first node coupled to ground and its secondnode coupled to the match line, and the second switch having its firstnode coupled to the first data line, its second terminal coupled to thecontrol terminal of the first switch, and its control node coupled tothe first data node, and the third switch having its first node coupledto ground and its second node coupled to the match line, and the fourthswitch having its first node coupled to the third data line, its secondterminal coupled to the control terminal of the third switch, and itscontrol node coupled to the third data node.
 26. The CAM device claim 24wherein the match circuit off the CAM cell comprises first, second,third, and fourth switches, each switch having a control node and firstand second nodes, the first switch having its control terminal coupledto the first data node and its first node coupled to ground, the secondswitch having its control terminal coupled to the first data line, itsfirst node coupled to the match line, and its second node coupled to thesecond node of the first transistor, and the third switch having itscontrol terminal coupled to the third data node and its first nodecoupled to ground, the fourth switch having its control terminal coupledto the third data line, its first node coupled to the match line, andits second node coupled to the second node of the third transistor. 27.The CAM device of claim 24 wherein the first and second bistablecircuits of the CAM cell comprise: a first switch having a first nodecoupled to a true data node, a second node coupled to ground, and acontrol node coupled to a not data node; a second switch having a firstnode coupled to the not data node, a second node coupled to ground, anda control node coupled to the true data node; a first resistor having afirst terminal coupled to the power supply and a second terminal coupledto the true data node; and a second resistor having a first terminalcoupled to the power supply and a second terminal coupled to the notdata node.
 28. The CAM device of claim 24 wherein the first and seconddata nodes of the CAM cell store complementary data, the first andsecond data lines are a pair of complementary data lines, the third andfourth data nodes store complementary data, and the third and fourthdata lines are a pair of complementary data lines.
 29. The CAM device ofclaim 24 wherein the search data and the data stored at the first datanode are mismatching when the logic level of each are the same.
 30. Acomputer system, comprising: a data input device; a data output device;a processor coupled to the data input and output devices; and a contentaddressable memory (CAM) device coupled to the processor, the CAM devicecomprising: an address bus; a control bus; a data bus; an addressdecoder coupled to the address bus; a read/write circuit coupled to thedata bus; and an array of CAM memory cells coupled to the addressdecoder, control circuit, and read/write circuit, the array comprising:a plurality of word lines; a plurality of data lines; a latch havingcomplementary data nodes capacitively coupled to ground; first andsecond access transistors, each having a gate coupled to one of theplurality of word lines and coupled between a data node of the latch anda respective data line of the plurality; and a match circuit coupled toone of the complementary data nodes of the latch, the match circuitdischarging a match line in response to a data value stored at the datanode to which the match circuit is coupled and compare data present onthe respective data line mismatching.
 31. The computer system of claim30 wherein the match circuit of the array of CAM memory cells comprises:first and second transistors coupled in series between the data lines towhich the first and second access transistors are coupled, the firsttransistor having a gate coupled to a first one of the data nodes andthe second transistor having a gate coupled to a second one of thecomplementary data nodes; and a discharge transistor coupled between thematch line and ground, and having a gate coupled to a node between thefirst and second transistors.
 32. The computer system of claim 30wherein the latch of the array of CAM memory cells is a first latch, thematch circuit is a first match circuit, and the static CAM array furthercomprises: a second latch having complementary data nodes capacitivelycoupled to ground, the first and second latches representing a singleCAM memory cell; third and fourth access transistors, each having a gatecoupled to the word line to which the first and second accesstransistors are coupled, the third and fourth access transistors coupledbetween a data node of the second latch and a respective data line ofthe plurality; and a second match circuit coupled to one of thecomplementary data nodes of the second latch, the match circuitdischarging the match line in response to a data value stored at thedata node to which the second match circuit is coupled and compare datapresent on the respective data line mismatching.
 33. The computer systemof claim 32 wherein the first and second match circuits of the array ofCAM memory cells comprise first and second switches, each switch havinga control node and first and second nodes, the first switch having itsfirst node coupled to ground and its second node coupled to the matchline, and the second switch having its first node coupled to the firstdata line, its second terminal coupled to the control terminal of thefirst switch, and its control node coupled to the first data node. 34.The computer system of claim 32 wherein the first and second matchcircuits of the array of CAM memory cells comprise first and secondswitches, each switch having a control node and first and second nodes,the first switch having its control terminal coupled to the first datanode and its first node coupled to ground, the second switch having itscontrol terminal coupled to the first data line, its first node coupledto the match line, and its second node coupled to the second node of thefirst transistor.
 35. The computer system of claim 30 wherein the latchof the array of CAM memory cells comprises: a first switch having afirst node coupled to a first of the complementary data nodes, a secondnode coupled to ground, and a control node coupled to the second datanode; a second switch having a first node coupled to the second datanode, a second node coupled to ground, and a control node coupled to thefirst data node; and first and second resistors, each resistor having afirst terminal coupled to the power supply and a second terminal coupledto a respective data node.
 36. A method for storing data in a contentaddressable memory, comprising: charging a first node of a firstcapacitor; activating a switch to couple a first node of a secondcapacitor to ground; maintaining a charge at the first node of the firstcapacitor.
 37. The method of claim 36 wherein maintaining a charge atthe first node comprises providing charge to the first node of the firstcapacitor through a resistive current path.
 38. The method of claim 36,further comprising coupling a resistive current path from a power supplyto ground.
 39. A method of storing data in a content addressable memory,comprising: charging a first capacitor; shunting a second capacitor; andmaintaining the charge on the first capacitor through a resistivecurrent path.
 40. The method of claim 39 wherein shunting the secondcapacitor comprises activating a switch to equalize the charge acrossthe second capacitor.
 41. A method for storing data in a contentaddressable memory, comprising: charging a first capacitor; setting abistable circuit to a first state; discharging a second capacitor inresponse to setting the bistable circuit; and maintaining the charge onthe first capacitor.
 42. The method of claim 41 wherein maintaining thecharge on the first capacitor comprises providing charge to the firstcapacitor through a resistive current path.